Modern electronics are more prone to suffering damage through electrostatic discharge (ESD) than their technological predecessors.
One reason for this is LCD TVs, mobile phones and other high-tech gadgets feature chip-sets below the 130 nanometer value. Electronic components in these devices are best suited for DC voltages less than 3.3 volts. Even worse, ESD protection requirements for these devices are 500 volts instead of the standard 8 kilo-volts.
How can you combat these ESD deficiencies? It starts with modifying internal components so ESD damage can be kept to a minimum.
A circuit board designer can employ four diffferent strategies for boosting ESD protection in an LCD circuit board:
- Reduce the length of the LESD.
- Reduce the length of the LGND
- Minimize the LIC and LPORT to their smallest possible ratios.
- Place buffering resistors between the ESD device and the IC if the other steps do not offer enough ESD protection.
Where an ESD device is located and how it is laid out is key to enhancing ESD protection. Both the LESD and LGND can increase the clamping voltage with a minor length increase. Taking each trace length from 0.5 centimeters to 1 centimeter, for example, can boost the overall clamping voltage by as much as 75 percent.
Putting the ESD device as close to the ESD point of entry as possible is an essential step. This makes the ratio of LPORT to LIC smaller. The LIC is non-linear, so it will create a buffer to the ESD pulse by making the voltage drop as it nears the IC.
Buffer resistors are needed if on-chip ESD structures are exposed to too much current. Adding 10Ω worth of buffering resistance can reduce peak current flow by as much as 50 percent.